Electronic circuit designs can be constructed, simulated, debugged, and translated into electronic hardware using a High Level Modeling System (HLMS). Typically, an HLMS is implemented as a software-based design tool. The HLMS provides blocks that can be combined to build an electronic circuit. A block refers to a high level software construct that represents a particular circuit function, such as multiplexing, addition, multiplication, or the like, e.g., a component. Blocks may have ports that can produce and consume signals, and may be arranged within the HLMS to form a circuit and/or system. Communication among the blocks can be represented by wires, or signals, that graphically link the blocks.
The circuit design may be simulated within the HLMS once it is constructed. Some HLMS tools further can generate a hardware implementation from the block representation of the circuit design. For example, an HLMS may generate the bitstream necessary to program a field programmable gate array (FPGA) or can generate the hardware description language (HDL) files necessary to specify the hardware design. One example of an HLMS is System Generator for DSP™ (System Generator) available from Xilinx, Inc. of San Jose, Calif. System Generator is a system level modeling tool that facilitates FPGA hardware design. System Generator provides cycle accurate and bit accurate simulation of circuit designs to be implemented within an FPGA.
Simulating a circuit design entails determining an execution order for the various blocks of the circuit design and executing each of the blocks according to that order. Typically, the circuit design to be simulated is represented as a directed graph in which vertices represent blocks, or circuit components, and arcs represent ports, or signals. To simulate a circuit design in a bit and cycle accurate manner, the blocks forming the circuit design must be executed in an order that reflects dependencies among the blocks as represented by the directed graph. The input of a given block, for example, may be affected by the outputs of one or more other blocks. A conventional HLMS typically visits each block of the circuit design on each clock cycle of the simulation. On each clock cycle of the simulation, a determination is made as to whether each block is to be executed when visited. Within a multi-rate, synchronous circuit design, not all blocks may execute on each clock cycle. With respect to multi-rate, synchronous circuit designs, this manner of scheduling can be inefficient and resource intensive.